PXB4219 Datasheet, PDF (73/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
4.5
Internal Clock Recovery Circuit (ICRC)
The Internal Clock Recovery Circuit (ICRC) may generate RTS values in upstream
direction and a 8.192, 2.048 or 1.544 MHz transmit clock in downstream direction. Each
port works independently using its own set of control registers and error counters. The
Cell delay variation is assumed to be less than +/- 4 ms.
According to ITU-T 432.1 [33] SRTS clock recovery is only defined for unstructured CES.
Therefore, ports supporting SRTS clock recovery have to be configured for only one
channel in unstructured CES with completely filled ATM cells.
The ICRC supports two Framer Interface formats
• FALC Mode (FAM, see Chapter 5.1.1) with a transmit clock frequency of 8.192 MHz
for both E1 and T1.
• Generic Interface Mode (GIM, see Chapter 5.1.2) with a transmit clock frequency of
2.048 MHz in case of E1 and 1.544 MHz in case of T1.
These modes can be selected via bits “om” in the Operation Mode Register (opmo, see
Chapter 7.24) and bit “gim” in the Internal Clock Recovery Circuit Configuration Register
(“icrcconf”, see Chapter 7.46).
Transmit clocks are generated by internal PLLs based on SRTS, ACM or both. The
method of transmit clock generation is selected via bits "srt" and "acm" in the
Configuration Register Downstream of Port N ("condN", see Chapter 7.47). Generation
of RTS values is enabled via bit “rtsg” in the Configuration Register Upstream of Port N
(“conuN”, see Chapter 7.51). If ACM is used, the corresponding RTS generator can be
kept disabled.
For communication between the ICRC and the rest of the chip a frame based protocol is
used. The internal interface as well as its protocol is the same as defined for the external
clock recovery interface (see Chapter 5.4).
The ICRC contains the following sub blocks:
Data Sheet
73
2002-05-06