PXB4219 Datasheet, PDF (95/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Interface Description
FTFRS[0:7]
RFCLK
Framer Transmit Frame Synchronization Pulse
FTFRS is generated at the beginning of timslot0 of every frame
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
The receive system clock and transmit system clock are both 8.192 MHz, and may be
independent from each other. The datarate is 2048 Mbit/s. This means that each bit lasts
for 4 clock cycles.
Data on the system internal highway is structured in frames of 256 bits every 125 µs. It
is transmitted in 32 slots numbered from 0 to 31 with slot 0 transmitted first. The data bits
of a slot are numbered from 1 to 8. The first transmitted bit ‘bit 1’ is the most significant
bit. Figure 23 shows the bit ordering.
Framer Receive Interface:
FRCLKn
FRDATn
FRMFBn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRFRSn
timeslot 31
Framer Transmit Interface:
FTCKOn
timeslot 0
timeslot 1
FTDATn
FTMFSn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FTFRSn
Figure 23
timeslot 31
Framer Interface in FAM
timeslot 0
timeslot 1
5.1.1.1 T1 Mode
In T1 mode (Pin E1/T1 = 0) there is one F-channel carrying the F-bit (Frame Alignement
Signal/Data Link (FS/DL)) and 24 data channels numbered from 0 to 23. When using the
Data Sheet
95
2002-05-06