PXB4219 Datasheet, PDF (130/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

band_width[3:0]
PXB4219 / PXB4220 / PXB4221
Memory Structure
sdt channel_mode[1:0] ref_slot
=1
next_slot_nr Next slot number
Number of the second slot of this channel. When no continuation slots
exist, the entry “next_slot_nr” should refer to the reference slot.
X = If pcfN[p_ces] = 1
snp_check SNP field check enable
X = If [aal0] = 1 or [sn_check] = 0
0 = Disabled
1 = Enabled
sn_check SN field check enable
X = If [aal0] = 1
0 = Disabled
1 = Enabled
sc_fast
SC algorithm select
X = If [aal0] = 1 or [sn_check] = 0
0 = Standard SC algorithm
1 = Fast SC algorithm
sdt_mfs
SDT multiframe pulse select
X = If [aal0] = 1 or [sdt] = 0 or pcfN[p_ces] = 1
0 = Start of structure is frame pulse
1 = Start of structure is multiframe pulse
sdt_oos_nr Number of SDT out of sync errors before re-initialization buffer
X = If [aal0] = 1 or [sdt] = 0
00 = Re-initialize after 1 out of sync error (recommended)
01 = Re-initialize after 2 out of sync error
10 = Re-initialize after 3 out of sync error
11 = Not allowed, IWE8 will not be able to re-initialize
sdt_par
SDT pointer parity check enable
X = If [aal0] = 1 or [sdt] = 0
0 = Disabled
Data Sheet
130
2002-05-06