PXB4219 Datasheet, PDF (13/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Figure 40 ACM Jitter Tolerance in E1 Mode with Jitter Attenuator . . . . . . . . . . 231
Figure 41 ACM Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . . . . . 232
Figure 42 ACM Jitter Tolerance in T1 Mode with Jitter Attenuator . . . . . . . . . . 232
Figure 43 SRTS Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . . 233
Figure 44 SRTS Jitter Tolerance in E1 Mode with Jitter Attenuator. . . . . . . . . . 234
Figure 45 SRTS Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . . . . 235
Figure 46 SRTS Jitter Tolerance in T1 Mode with Jitter Attenuator . . . . . . . . . . 235
Figure 47 ACM Jitter Transfer in E1 Mode without Jitter Attenuator . . . . . . . . . 236
Figure 48 ACM Jitter Transfer in E1 Mode with Jitter Attenuator . . . . . . . . . . . . 237
Figure 49 ACM Jitter Transfer in T1 Mode without Jitter Attenuator . . . . . . . . . 238
Figure 50 ACM Jitter Transfer in T1 Mode with Jitter Attenuator . . . . . . . . . . . . 238
Figure 51 SRTS Jitter Transfer in E1 Mode without Jitter Attenuator . . . . . . . . 239
Figure 52 SRTS Jitter Transfer in E1 Mode with Jitter Attenuator . . . . . . . . . . . 240
Figure 53 SRTS Jitter Transfer in T1 Mode without Jitter Attenuator . . . . . . . . 241
Figure 54 SRTS Jitter Transfer in T1 Mode with Jitter Attenuator . . . . . . . . . . . 241
Figure 55 Input/Output Waveforms for AC Measurements . . . . . . . . . . . . . . . . 247
Figure 56 Clock and Reset Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . 247
Figure 57 Framer Receive Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . . 248
Figure 58 Framer Transmit Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . . 250
Figure 59 Framer Receive Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . . . 251
Figure 60 Framer Transmit Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . . 252
Figure 61 Framer Interface Timing for SYM 2.048 MHz . . . . . . . . . . . . . . . . . . 254
Figure 62 Framer Interface Timing in SYM 8.192 MHz . . . . . . . . . . . . . . . . . . . 255
Figure 63 Framer Interface Timing in EC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 64 Setup and hold time definition (single- and multi PHY) . . . . . . . . . . . 257
Figure 65 Tri-state timing (multi-PHY, multiple devices only). . . . . . . . . . . . . . . 257
Figure 66 Timing of the IMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 67 Clock Recovery Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . 261
Figure 68 Intel Mode Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 262
Figure 69 Intel Mode Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 263
Figure 70 Motorola Mode Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 71 RAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 72 Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . 266
Figure 73 Package Outline: P-BGA-256 (Plastic Metric Quad Flat Package) 273
Figure 74 Structure of the AAL1 SAR-PDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 75 Informative and Example Algorithm State Machine (Fig. III.2/I.363.1) 276
Figure 76 The Concept of Synchronous Residual Time Stamp (SRTS) (Fig. 5/
I.363.1) 278
Figure 77 Generation of Residual Time Stamp (RTS) (Fig.6/ I.363.1) . . . . . . . . 279
Figure 78 Example Multiframe Structure for 3x64 Kbit/s E1 with CAS. . . . . . . . 282
Data Sheet
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2002-05-06