PXB4219 Datasheet, PDF (28/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 2
UTOPIA Interface (36 pins) (cont’d)
Pin No. Symbol
Input (I) Function
Output (O)
V10
RXCLAV
Slave: O UTOPIA Receive Cell Available
Master: I Slave: RXCLAV is an active high signal
PDA
asserted by the PHY layer to indicate that it
has data available for transfer to the ATM
layer.
Master: RXCLAV is an active high signal
asserted by the ATM layer to indicate that it
has data available for transfer to the PHY
layer.
V13
RXCLK
I
UTOPIA Receive Clock
Transfer/synchronization clock from the
ATM layer to the PHY layer for
synchronizing transfers on RXDAT[0:7].
W13
RXENB
Slave: I
Master: O
PUA
UTOPIA Receive Enable
Slave: Active low signal asserted by the
ATM layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
Master: Active low signal asserted by the
PHY layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
V4, U5, Y3, RXADR[4:0] I
Y4, V5
PUA
UTOPIA Receive Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to select the appropriate
MPHY device. RXADR[4] is the MSB.
Y6, V7,
W7, Y7,
V8, W8,
Y8, U9
TXDAT[7:0]
I
PUA
UTOPIA Transmit Data Bus
Byte-wide true data driven from ATM to
PHY layer. TXDAT[7] is the MSB.
V9
TXPTY
I
UTOPIA Transmit Odd Parity Bit
PUA
TXPTY is the odd parity bit over TXDAT[0:7]
driven by the ATM layer.
W6
TXSOC
I
UTOPIA Transmit Start-of-Cell
PDA
Active high signal asserted by the ATM
layer when TXDAT[0:7] contains the first
valid byte of the cell.
Data Sheet
28
2002-05-06