PXB4219 Datasheet, PDF (202/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Register Description
7.46
Internal Clock Recovery Circuit Configuration Register
(icrcconf)
Read/Write Address 00103_H
Reset value: 0020_H
15
8
Not used
gim
7
0
ds1
parc
pdcri
srst
lptd
lptu
lprd
lpru
gim
ds1
parc
pdcri
srst
lptd
Generic interface mode
0 = FAM: 8.192 MHz is expected/generated.
1 = GIM: 2.048 MHz (E1) or 1.544 MHz (T1) expected/generated.
DS1 Mode
0 = E1: The receive clocks are divided to 2.048 MHz. Output clocks
are 8.192 MHz in case of FAM or 2.048 MHz in case of GIM.
1 = T1: The receive clocks are divided to 1.544 MHz. Output clocks
are 8.192 MHz in case of FAM or 1.544 MHz in case of GIM.
Parity Check
Inverts all parity bits in the ICRC. All enabled parity checkers will
generate interrupts
0 = Disabled
1 = Enabled
Power Down Clock Recovery Interface
0 = Normal operation
1 = The internal clock recovery interface is put in power down mode.
No data is received, no errors are generated and the parity check
is disabled.
Software Reset
The bit srts is set by the software, but reset by the ICRC. Reading this
bit will always give the Reset value: “0”.
0 = Normal operation
1 = Reset ICRC
Loop back clock recovery interface transmitted data downstream
Data Sheet
202
2002-05-06