PXB4219 Datasheet, PDF (142/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Memory Structure
For reading the Interrupt Queue refer to Chapter 4.6.3.
Each interrupt queue entry identifies a particular statistics counter that has reached its
threshold value. The format of the interrupt queue entries is as follows:
31
23
15
iq_ne
7
not used
channel_nr[3:0]
Not used
Not used
24
16
port_nr
[2:0]
counter_nr[3:0]
8
channel_
nr[4]
0
iq_ne
interrupt queue not empty
0 = interrupt queue is empty, no further entries
1 = interrupt queue is not empty, further entries can be read
6.2.4 Timers
Read/write Address 26000_H to 2601F_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 16 × 32 bits: 2 timer sets x 8 timers
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 1 1 0 0 0 0 0 0 0 0 timer_nr[3:0] 0
timer_nr[3]
timer_nr
[2:0]
Timer number
Selects the timer set
0 = Timer set 2 indicated on MPIR2
1 = Timer set 1 indicated on MPIR1
Timer number
Number of the associated timer
Data Sheet
142
2002-05-06