PXB4219 Datasheet, PDF (214/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Register Description
7.56
ICRC Parity Errors at Clock Recovery Interface (per)
Destructive read Address 00110_H
Reset value: 0000_H
15
8
perd[7:0]
7
0
peru[7:0]
perd
peru
Parity Errors at the Clock Recovery Interface Downstream Pin SDOD
This field counts the amount of parity errors at the internal clock recovery
interface. In case there are more than 255 errors, the value is kept
Parity Errors at the Clock Recovery Interface Upstream Pin SDI
This field counts the amount of parity errors at the internal clock recovery
interface. In case there are more than 255 errors, the value is kept
Note: A synchronization error (scri) generates a random number of parity errors
Data Sheet
214
2002-05-06