PXB4219 Datasheet, PDF (27/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Pin Descriptions
Table 1
Pin No.
C20, B17,
D14, D12,
C10, C8,
C6, A2
E17, C17,
B15, C12,
D10, A7,
B5, C3
L1
Generic Framer Interface (73 pins) (cont’d)
Symbol
Input (I) Function
Output (O)
FTMFS[7:0] O
PUA
Framer Transmit Multiframe
Synchronization
Indication that a new multi-/superframe is
available on the transmit side of the framer
interface
FTFRS[7:0]
O
PUA
Framer Transmit Frame Synchronization
Pulse
Indication that a new frame is available on
the transmit side of the framer interface
RFCLK
I
Reference Clock
SYM and EC mode: Central framer interface
clock for all framer ports
FAM and GIM: Optional SRTS/ACM
reference or emergency clock for the framer
receive interface in case of clock failure
2.2.2 UTOPIA Interface
Table 2
Pin No.
Y11, W11,
V11, U11,
Y12, W12,
V12, U12
Y13
W10
UTOPIA Interface (36 pins)
Symbol
Input (I) Function
Output (O)
RXDAT[7:0] O
PUA
UTOPIA Receive Data Bus
Byte-wide data driven from PHY to ATM
layer. RxData[7] is the MSB.
RXPTY
RXSOC
O
PUA
O
PDA
UTOPIA Receive Odd Parity Bit
Odd parity for RXDAT[0:7] driven by the
PHY layer.
UTOPIA Receive Start-of-Cell
Active high signal asserted by the PHY layer
when RXDAT[0:7] contains the first valid
byte of a cell.
Data Sheet
27
2002-05-06