PXB4219 Datasheet, PDF (278/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Appendix
12.2
Synchronous Residual Time Stamp SRTS
This sub chapter contains a short description of the SRTS method, as defined in [12] and
[31].
The SRTS algorithm is used to measure the frequency deviation of a data stream which
is packetized in ATM cells. This frequency is coded in 4 bits and sent to the receiver. At
the receiver, the correct frequency is regenerated.
The 4 RTS bits are spread over 8 ATM cells. These 8 ATM cells contain 8 x 47 byte x 8
bit/byte = 3008 bits of data. In case of an E1 line, the data arrives with 2.048 Mbit/s, thus
after 3008 bit / 2.048 Mbit/s = 1,46875 ms a complete RTS value is received. The
frequency of generated RTS values is 681 Hz.
The RTS value is calculated in the following way:
In N = 3008 cycles of Fdata, we have Mq cycles of the reduced network clock. The
reduced network clock Fnx has to fulfil the following equation: 1 <= Fnx / Fdata < 2. This
defines the value of x in the equation: Fnx = 8 kHz X 19440 / 2^x. For a full E1 line Fdata
= 2.048 MHz, x = 6 and Fnx = 2.43 MHz. The maximum input frequency deviation of 200
ppm (E1 lines: less than 50 ppm) of the data clock translates in a deviation from Mq. At
the receiving side, the same network clock is available and the numbers N and x are
known. As a result, the nominal value Mnom of Mq is known, and only the deviation from
Mnom has to be transmitted. The number of bits to transmit the deviation (p = 4) has to
be sufficient for the maximum frequency deviation.
N cycles T seconds
tolerance
f_s
t
M_q
M_min M_nom M_max
f_nx
t
y
y
2^p
Figure 76
T1817630-92
The Concept of Synchronous Residual Time Stamp (SRTS) (Fig. 5/
I.363.1)
Data Sheet
278
2002-05-06