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PXB4219 Datasheet, PDF (63/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines | |||
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PXB4219 / PXB4220 / PXB4221
Operational Description
The bit âsdt_parâ in the âAAL Transmit Reference Slotâ allows to disable the verification
of the parity bit in the pointer field.
For multiframe based SDT the bit âsdt_mfsâ in the âAAL Transmit Reference Slotâ has to
be set.
4.4.1.6 CAS Conditioning and Freezing Downstream
An internal signalling buffer holds the CAS bits. In case of buffer underflow or pointer
mismatch the IWE8 provides downstream CAS conditioning and freezing according to
Bellcore TR-NWT-000170 [14].
The selection between both is done individually for each channel via Bit âcond_enâ in the
âAAL Transmit Conditioning Slotâ of RAM4. Values for conditioning can be selected via
the âcond_down_nibbleâ bits in the same register.
The spare and alarm indication bits of the first E1 frame can be programmed by setting
bits cas0portN in the registers âcas1â and âcas2â. The CAS information of idle time slots
can be chosen by setting bits in the register âcas3â.
4.4.1.7 Insertion of Dummy Cells at Cell Loss
Upon cell loss detection, the sequence count algorithm will insert dummy cells into the
Reassembly Buffer to maintain bit count integrity. The maximum amount of
consecutively inserted cells is 6.
These dummy cells are physically inserted when reading the Reassembly Buffer. The
Reassembly Buffer itself contains only control field in front of the payload of the next
accepted cell, indicating the amount of dummy cells to be inserted.
Inserted dummy cells are not taken into account for the ACM Reassembly Buffer filling
level calculation. This means that the buffer filling level is incorrect as long as dummy
cells are physically inserted.
The data octet used for the dummy cells is the byte-pattern selected by the âstarv_bpslctâ
field of the âAAL transmit reference slotâ of RAM3.
4.4.1.8 Reassembly Buffer
The purpose of the Reassembly Buffer is to compensate the Cell Delay Variation (CDV)
of the ATM network.
It is located in external RAM providing 512 byte of memory for each timeslot, totalling to
128 KB for 8 ports with 32 timeslots each. The buffer for each timeslot consists of 8
memory blocks with 64 octets:
Buffer size = 8 Ports x 32 Channels x 8 Blocks x 64 Octets
[2]
Data Sheet
63
2002-05-06
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