HYB18T256400AF Datasheet, PDF (82/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
8.3 Input and Data Setup and Hold Time
8.3.1 Timing Definition for Input Setup (tIS) and Hold Time (tIH)
Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a ris-
ing signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH)
is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal
applied to the device under test..
CK
CK
t _IS t _IH
tIS tIH
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
8.3.2 Timing Definition for Data Setup (tDS) and Hold Time (tDH)
Data input setup time (tDS) with differential data strobe enabled MR[bit10]=0, is referenced from the input signal
crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal
crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under
test. DQS/DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data input hold time (tDH) with
differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the
differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a fall-
ing signal applied to the device under test. DQS/DQS signals must be monotonic between VIL(dc)max and
VIH(dc)min.
Data input setup time (tDS) with single-ended data strobe enabled MR[bit10]=1, is referenced from the input sig-
nal crossing at the VIH(ac) level to the data strobe crossing VREF for a rising signal, and from the input signal
crossing at the VIL(ac) level to the single-ended data strobe crossing VREF for a falling signal applied to the
device under test. Data input hold time (tDH) with single-ended data strobe enabled MR[bit10]=1, is referenced
from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VREF for a rising signal
and VIH(dc) to the single-ended data strobe crossing VREF for a falling signal applied to the device under test.
DQS
DQS
DQS
t _DS t _DH
tDS tDH
Differential Input
Waveform
Single-ended Input
Waveform
V _REF
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Page 82
Rev. 1.02 May 2004
INFINEON Technologies