HYB18T256400AF Datasheet, PDF (8/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
1.4.3 Package Pinout for x16 components 84 pins, FBGA Package (top view)
1
2
3
7
8
9
VDD
NC
VSS
A
VSSQ UDQS VDDQ
UDQ6 VSSQ UDM
B
UDQS VSSQ UDQ7
VDDQ UDQ1 VDDQ
C
VDDQ UDQ0 VDDQ
UDQ4 VSSQ DQ3
D
UDQ2 VSSQ UDQ5
VDD
NC
VSS
E
VSSQ LDQS VDDQ
LDQ6 VSSQ LDM
F
LDQS VSSQ LDQ7
VDDQ LDQ1 VDDQ
G
VDDQ LDQ0 VDDQ
LDQ4 VSSQ LDQ3
H
LDQ2 VSSQ LDQ5
VDDL VREF VSS
J
VSSDL CK
VDD
CKE
WE
K
RAS
CK
ODT
RFU
BA0
BA1
L
CAS
CS
A10
A1
M
A2
A0
VDD
VSS
A3
A5
N
A6
A4
A7
A9
P
A11
A8
VSS
VDD
A12 NC,(A14)
R
NC,(A15) NC,A13)
Notes:
1) UDQS/UDQS is data strobe for upper byte, LDQS/LDQS is data strobe for lower
byte
2) UDM is the data mask signal for the upper byte UDQ0~UDQ7,
LDM is the data mask signal for the lower byte LDQ0~LDQ7
3) NC,(A13), NC, (A14) and NC, (A15) are additional address pins for future gener-
ation DRAMs and are not connected on this component.
4) Ball position G1 “RFU” will be used for BA2 on 1Gbit memory densities and
higher
Page 8
Rev. 1.02 May 2004
INFINEON Technologies