HYB18T256400AF Datasheet, PDF (52/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.8.4 Concurrent Auto-Precharge
DDR2 devices support the “Concurrent Auto-Precharge” feature. A Read with Auto-Precharge enabled, or a Write
with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does
not interrupt the read or write data transfer, and all other related limitations (e.g. contention between Read data
and Write data must be avoided externally and on the internal data bus.
The minimum delay from a Read or Write command with Auto-Precharge enabled, to a command to a different
bank, is summarized in the table below. As defined, the WL = RL - 1 for DDR2 devices which allows the command
gap and corresponding data gaps to be minimized.
From Command
To Command
(different bank,
non-interrupting command)
Minimum Delay with
Concurrent Auto-Pre-
charge Support
Units Note
Read or Read w/AP
(CL -1) + (BL/2) + tWTR tCK
WRITE w/AP
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
1)
Read or Read w/AP
BL/2
tCK
Read w/AP
Write or Write w/AP
BL/2 + 2
tCK
Precharge or Activate
1
tCK
1)
Note:
1) This rule only applies to a selective Precharge command to another banks, a Precharge-All command is
illegal
Page 52
Rev. 1.02 May 2004
INFINEON Technologies