HYB18T256400AF Datasheet, PDF (39/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.6.5 Write Data Mask
One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for x16
components are supported on DDR2 SDRAM’s, consistent with the implementation on DDR SDRAM’s. It has
identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally
loaded identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is
high during a write burst coincident with the write data, the write data bit is not written to the memory. For x8 com-
ponents the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1).
.
Write Data Mask Timing
DQS,
DQS
t _DQSH t DQSL
DQS
DQS
t_WPRE
t _WPST
DQ
Din
Din
Din
Din
t _DS
t _DH
DM
don't care
.
Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CM D _{W R ITE A}
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
<= tDQSS
WL = RL-1 = 2
tW R
DQ
DIN A0 DIN A1 DIN A2 DIN A3
NOP
P re c h a rg e
Bank A
A c tiv a te
tR P
DM
DM
Page 39
Rev. 1.02 May 2004
INFINEON Technologies