HYB18T256400AF Datasheet, PDF (48/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Examples:
Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
DQS,
DQS
DQ
P osted CAS
R EAD w/AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 ="high"
AL + BL/2
Auto-Precharge Begins
AL = 2
CL = 3
RL = 5
tRAS
tRCmin.
tRP
Dout A0 Dout A1 Dout A2 Dout A3
Bank
A c tiv a te
BR-AP5231
Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit):
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Posted CAS
NOP
REA D w/AP
NOP
NOP
NOP
NOP
NOP
Bank
A c tiv a te
NOP
DQS,
DQS
A10 ="high"
tRAS(min)
Auto-Precharge Begins
AL = 2
CL = 3
tRP
RL = 5
DQ
Dout A0 Dout A1 Dout A2 Dout A3
tRC
BR-AP5232
Page 48
Rev. 1.02 May 2004
INFINEON Technologies