HYB18T256400AF Datasheet, PDF (31/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Read followed by a write to the same bank, Activate to Read delay = tRCDmin:
AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
01 2
CK, CK
CMD
DQS,
DQS
Activate
Bank A
DQ
tRCD
3 4 5 6 7 8 9 10 11
AL = 0
Read
Bank A
CL = 3
Write
Bank A
WL = RL -1 = 2
RL = AL + CL = 3
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
PostCAS2
Read followed by a write to the same bank, Activate to Read delay > tRCDmin:
AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
01
2 34
5
6
7
8 9 10
CK, CK
CMD
DQS,
DQS
Activate
Bank A
tRCD > tRCDmin.
Read
Bank A
DQ
RL = 4
WL = 3
Write
Bank A
Dout0 Dout1 Dout2 Dout3
11 12 13
Din0 Din1 Din2 Din3
PostCAS5
Page 31
Rev. 1.02 May 2004
INFINEON Technologies