HYB18T256400AF Datasheet, PDF (60/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.13 Asynchronous CKE Low Reset Event
In a given system, Asynchronous Reset event can occur at any time without prior knowledge. In this situation,
memory controller is forced to drop CKE asynchronously low, immediately interrupting any valid operation. DRAM
requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “low” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If
this event occurs, the memory controller must satisfy a time delay (tdelay) before turning off the clocks. Stable
clocks must exist at the input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as
described the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the
initialization sequence. See AC timing parametric table for tdelay specification.
Asynchronous CKE Low Event
stable clocks
CK, CK
tdelay
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
Page 60
Rev. 1.02 May 2004
INFINEON Technologies