HYB18T256400AF Datasheet, PDF (74/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
6.2 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
Parameter
Symbol
-5
DDR2 -400
-3.7
DDR2 -533
-3S
-3
DDR2 - 667 DDR2 - 667
Unit
3-3-3
4-4-4
5-5-5
4-4-4
CAS Latency
CL(IDD)
3
4
5
4
tCK
Clock Cycle Time
tCK(IDD)
5
3.75
3
3
ns
Active to Read or Write delay
tRCD(IDD)
15
15
15
12
ns
Active to Active / Auto-Refresh command
period
tRC(IDD)
60
60
60
57
ns
Active bank A to Active
bank B command delay
1 kB page size tRRD(IDD)
7.5
7.5
7.5
7.5
ns
Active to Precharge Command
tRASmin(IDD)
tRASmax(IDD)
45
70000
45
70000
45
70000
45
ns
70000
ns
Precharge Command Period
tRP(IDD)
15
15
15
12
ns
Auto-Refresh to Active / Auto-Refresh com-
mand period
tRFC(IDD)
75
75
75
75
ns
6.3 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current
consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long a
ODT is enabled during a given period of time.
ODT current per terminated input pin:
EMRS(1) State _{min. typ. max.} Unit
Enabled ODT current per DQ
A6 = 0, A2 = 1 tbd. tbd. 7.5 mA/DQ
added IDDQ current for ODT enabled;
IODTO
ODT is HIGH; Data Bus inputs are FLOATING
A6 = 1, A2 = 0 tbd. tbd. 3.75 mA/DQ
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
A6 = 0, A2 = 1 tbd. tbd.
IODTT
A6 = 1, A2 = 0 tbd. tbd.
15 mA/DQ
7.5 mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
Page 74
Rev. 1.02 May 2004
INFINEON Technologies