HYB18T256400AF Datasheet, PDF (45/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD _{READ A}
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clks + 1
CL = 4
RL = 4
> = tR A S
NOP
NOP
P re ch a rg e
NOP
tR P
NOP
Bank A
A ctivate
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
>=tR TP
first 4-bit prefetch
second 4-bit prefetch
BR-P404(8)
Page 45
Rev. 1.02 May 2004
INFINEON Technologies