HYB18T256400AF Datasheet, PDF (50/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.8.2 Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2
SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery
time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Pre-
charge from the completion of the write burst may be reactivated if the following two conditions are satisfied.
(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
In DDR2 SDRAM’s the write recovery time delay (WR) has to be programmed into the MRS mode register. As
long as the analog twr timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles.
Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL.
Examples:
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
CMD
DQS,
DQS
DQ
W RITE
w /A P
NOP
NOP
A10 ="high"
NOP
NOP
NOP
Completion of the Burst Write
NOP
NOP
Bank A
A c tiv a te
Auto-Precharge Begins
WL = RL-1 = 2
DIN A0 DIN A1 DIN A2 DIN A3
WR
tDAL
tRCmin.
>=tRASmin.
tRP
BW-AP223
Page 50
Rev. 1.02 May 2004
INFINEON Technologies