HYB18T256400AF Datasheet, PDF (28/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.5 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row addresses A0 through A12
are used to determine which row to activate in the selected bank for x4 and x8 organised components. For x16
components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied
before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2
SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a
R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be
programmed into the device to delay the R/W command which is internally issued to the device. The additive
latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported.
Once a bank has been activated it must be precharged before another Bank Activate command can be applied to
the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum
time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum
time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD).
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2
T0
T1
T2
T3
T4
Tn
Tn+1
Tn+2
Tn+3
CK, CK
Internal RAS-CAS delay tRCDmin.
Address
Bank A
Bank A
Row Addr. Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A to Bank B delay tRRD.
additive latency AL=2
Read A
Begins
Bank A
NOP
Bank B
Bank A
Addr.
Addr.
Row Addr.
Command ^{Bank A}
Activate
Posted CAS
Read A
Bank B
Activate
Posted CAS
Read B
tRAS Row Active Time (Bank A)
tCCD
Bank A
NOP
Precharge
Bank B
Precharge
Bank A
Activate
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
ACT
Page 28
Rev. 1.02 May 2004
INFINEON Technologies