HYB18T256400AF Datasheet, PDF (16/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
MRS Mode Register Operation Table (Address Input For Mode Set)
BA2
A13~
BA1 BA0 _A15 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0* 0* 0*
0* PD
WR
DLL TM CAS Latency BT Burst Length Mode
Register
A8 DLL Reset
0
No
1
Yes
A7
Mode
0
Normal
1
Test
Burst Type
0 Sequential
1 Interleave
A2 A1 A0 Burst Length
010
4
011
8
A12 ^{Active Power-Down}
Mode Select
0 Fast exit (use tXARD)
1 Slow exit (use tXARDS)
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MRS
EMRS(1)
EMRS(2):
Reserved
EMRS(3):
Reserved
A11 A10 A9
000
001
010
011
100
101
110
111
WR **)
Reserved
2
3
4
5
6
Reserved
Reserved
A6 A5 A4 Latency
0 0 0 Reserved
0 0 1 Reserved
0
1
0 2 (optional) ***)
011
3
100
4
101
5
1 1 0 Reserved
1 1 1 Reserved
*) Must be programmed to 0 when setting the mode register. A13 ~ A15 and BA2 are reserved for future use
and must be programmed to 0 when setting the mode register MRS
**) The programmability of WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time
when the device starts precharge internally. WR must be programmed to fulfill the minimum retirement for
the analogue tWR timing.
***) CAS Latency = 2 is implemented in this design, but functionality is not tested and guaranteed.
Page 16
Rev. 1.02 May 2004
INFINEON Technologies