HYB18T256400AF Datasheet, PDF (62/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
Current State²
Previous
Cycle ¹
(N-1)
Current
Cycle ¹
(N)
L
L
Power-Down
L
H
L
L
Self Refresh
L
H
Bank(s)
Active
H
L
H
L
All Banks Idle
H
L
Any State other
than listed above
H
H
Command (N) ^3,12
RAS, CAS, WE, CS
Action (N) ³
Notes
X
DESELECT or NOP
X
DESELECT or NOP
Maintain Power-Down
Power-Down Exit
Maintain Self Refresh
Self Refresh Exit
11, 13, 15
4, 8, 11, 13
11, 15
4, 5, 9
DESELECT or NOP
Active Power-Down Entry _{4,8,10,11, 13}
DESELECT or NOP
AUTOREFRESH
Precharge Power-Down Entry
Self Refresh Entry
4,8,10,11
6, 9, 11, 13
Refer to the Command Truth Table
7
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period.
Read commands may be issued only after tXSRD (200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELCT only.
10. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
Precharge or Refresh operations are in progress. See section 2.8 “Power Down” and section 2.7.2 “Self Refresh Com-
mand” for a detailed list of restrictions.
11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
the refresh requirements.
14. CKE must be maintained high while the device is in OCD calibration mode.
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven
high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
16. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
3.3 Data Mask (DM) Truth Table
Name (Function)
Write Enable
Write Inhibit
DM
DQs Notes
L
Valid
1
H
X
1
1. Used to mask write data; provided coincident with the corresponding data.
Page 62
Rev. 1.02 May 2004
INFINEON Technologies