HYB18T256400AF Datasheet, PDF (4/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
1.1 Ordering Information
Part Number
CAS
Latency
Clock
(MHz)
Speed
Sort
DRAM Organisation
Package
HYB18T256400AF(L)-5
4 banks x 16 Mbits x 4 60 pin FBGA
HYB18T256800AF(L)-5
3, 4 & 5
200 DDR2-400 4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160AF(L)-5
4 banks x 4 Mbits x 16 84 pin FBGA
HYB18T256400AF(L)-3.7
4 banks x 16 Mbits x 4 60 pin FBGA
HYB18T256800AF(L)-3.7
4&5
266 DDR2-533 4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160AF(L)-3.7
4 banks x 4 Mbits x 16 84 pin FBGA
HYB18T256400AF(L)-3
4 banks x 16 Mbits x 4 60 pin FBGA
HYB18T256800AF(L)-3
4&5
4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160AF(L)-3
HYB18T256400AF(L)-3S
4 banks x 4 Mbits x 16 84 pin FBGA
333 DDR2-667
4 banks x 16 Mbits x 4 60 pin FBGA
HYB18T256800AF(L)-3S
5
4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160A(L)-3S
4 banks x 4 Mbits x 16 84 pin FBGA
Notes:
1) For product nomenclature see section 10 of this datasheet
2) Versions with an “L” in the part numbers are Low Power versions of the standard component with reduced IDD6 Self-Refresh
current. See section 6.1 for IDD current specifications.
3) All FBGA packages are lead-free.
1.2 Pin Description
1.2.1 x4 Components
Symbol
A0~A12
A0~A9,A11
BA0, BA1
A10/AP
CS
RAS
CAS
WE
DQ0~DQ3
CKE
CK, CK
DM
Function
Row Address Inputs
Column Address Inputs
Bank Address Inputs
Column Address Input
for Auto-Precharge
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Inputs/Outputs (x4)
Clock Enable
Differential Clock Inputs
Data Input Mask
Symbol
DQS, DQS
NC
VDD
VSS
VDDQ
VSSQ
VDDL
VSSDL
VREF
ODT
RFU
NC
Function
Differential Data Strobes
No Connection (Chip to Pin)
Supply Voltage
Ground
Supply Voltage for DQ
Ground for DQs
Supply Voltage for DLL
Ground for DLL
Reference Voltage for SSTL
Inputs
On Die Termination Enable
Reserved for future use
Not Connected
Page 4
Rev. 1.02 May 2004
INFINEON Technologies