HYB18T256400AF Datasheet, PDF (78/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
7.2 Timing Parameter by Speed Grade - DDR2-667
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V) (notes 1-4)
Symbol
Parameter
-3S
DDR2-667-555
min.
max
-3
DDR2-667-444
min.
max
Unit Notes
tRP Precharge command period
15
-
12
-
ns
tRRD
Active bank A to Active bank B
command period
x4, x8 & x16
(1k page size)
7.5
-
7.5
-
ns
tCCD CAS A to CAS B Command Period
2
2
tCK
tWR Write recovery time
15
-
15
-
ns
tDAL Auto-Precharge write recovery + precharge time
WR+tRP
-
WR+tRP
-
tCK 14
tWTR Internal Write to Read command delay
7.5
-
7.5
-
ns 15
tRTP Internal Read to Precharge command delay
7.5
-
7.5
-
ns
tXARD
Exit power down to any valid command
(other than NOP or Deselect)
2
-
2
-
tCK 16
tXARDS
Exit active power-down mode to Read command
(slow exit, lower power)
6 - AL
-
6 - AL
-
tCK 16
tXP
Exit precharge power-down to any valid command
(other than NOP or Deselect)
2
-
2
-
tCK
tXSRD Exit Self-Refresh to read command
200
-
200
-
tCK
tXSNR Exit Self-Refresh to non-Read command
tRFC+10
tRFC+10
ns
tCKE CKE minimum high and low pulse width
3
3
tCK
0^oC - 85^oC
-
7.8
-
7.8
µs
tREFI Average periodic refresh Interval
85^oC - 95^oC
-
3.9
-
19
3.9
µs
tOIT OCD drive mode output delay
0
12
0
12
tDELAY
Minimum time clocks remain ON after CKE asynchro-
nously drops LOW
tIS+tCK+tIH
-
tIS+tCK+tIH
-
ns
ns 17
Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
Page 78
Rev. 1.02 May 2004
INFINEON Technologies