HYB18T256400AF Datasheet, PDF (32/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.6.2 Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory
locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst
length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address
ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst
length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or
interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write
operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is pro-
grammed. For burst interruption of a read or write burst when burst length = 8 is used, see the “Burst Interruption
“section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices.
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
x00
0, 1, 2, 3
0, 1, 2, 3
x01
4
x10
1, 2, 3, 0
2, 3, 0, 1
1, 0, 3, 2
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
8
100
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Notes: 1) Page size for all 256Mbit components is 1 kByte
2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR
or DDR components
Page 32
Rev. 1.02 May 2004
INFINEON Technologies