HYB18T256400AF Datasheet, PDF (80/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
7.4 Notes for Electrical Characteristics & AC Timing
1. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a dif-
ferential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew
rates see Section 8 of this datasheet.
2. The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS,RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, tIS, tiH, tDS, tDH is VREF.
For tIS, tiH, tDS, tDH input reference levels see section 8.3 of this datasheet
3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as LOW.
4. The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements.
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH.
6. For input frequency change during DRAM operation, see the 2.11 section of this datasheet.
7. For timing definition, slew rate and slew rate derating see Section 8.3
8. For timing definition, slew rate and slew rate derating see Section 8.3
9. The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device out-
put is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access
time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to
production test.
10. The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
11. tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command
which is equal to 9 * tREFI
12. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
13. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge.
Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not neces-
sary anymore.
14. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MRS.
15. tWTR is at least two clocks independent of operation frequency.
16. User can choose two different active power-down modes for additional power saving via MRS address bit A12.
In “standard active power-down mode” (MRS, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active
power-down mode” (MRS, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
17. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock fre-
quency change during power-down, a specific procedure is required as describes in section 2.12.
18. Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output slew rate mis-match between DQS / DQS and associated DQ in any given cycle.
19. The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85^oC and 95^oC.
20. ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND.
21. ODT turn off time min. is when the device starts to turn off ODT resistance
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Page 80
Rev. 1.02 May 2004
INFINEON Technologies