HYB18T256400AF Datasheet, PDF (61/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
3. Truth Tables
3.1 Command Truth Table
Function
CKE
Previous Current
Cycle
Cycle
(Extended) Mode Register Set
H
H
Auto-Refresh
H
H
Self-Refresh Entry
H
L
Self-Refresh Exit
L
H
Single Bank Precharge
H
H
Precharge all Banks
H
H
Bank Activate
H
H
Write
H
H
Write with Auto-Precharge
H
H
Read
H
H
Read with Auto-Precharge
H
H
No Operation
H
X
Device Deselect
H
X
Power Down Entry
H
L
Power Down Exit
L
H
CS
RAS CAS
WE
BA0
BA1
A12-A11
A10
A9 - A0
Notes
L L L L BA
OP Code
1, 2
L L LHX
X
X
X
1
L L LHX
X
X
X
1
HXXXX
X
X
X
1
L L H L BA
X
L
X
1,2
L LHLX
X
H
X
1
L L H H BA
Row Address
1, 2
L H L L BA Column L Column 1,2,3
L H L L BA Column H Column 1,2,3
L H L H BA Column L Column 1,2,3
L H L H BA Column H Column 1,2,3
L HHHX
X
X
X
1
HXXXX
X
X
X
1
HXXX
X
X
X
X
1,4
L HHH
HXXX
X
X
X
X
1,4
L HHH
1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
2. Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended) Mode
Register.
3. Burst reads or writes at BL = 4 cannot be terminated. See sections “Reads interrupted by a Read” and “Writes inter-
rupted by a Write” in section 2.4.6 for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by
the refresh requirements outlined in section 2.7.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM
must be powered down and then restarted through the specified initialization sequence before normal operation can
continue.
Page 61
Rev. 1.02 May 2004
INFINEON Technologies