HYB18T256400AF Datasheet, PDF (38/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
W R ITE A
NOP
Post CAS
W RITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3
SBR
The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Seamless Burst Write Operation: RL = 3, WL = 2, BL = 8, non interrupting
T0
T1
T2
T3
T4
T5
T6
CK, CK
CM D _{W R ITE A}
NOP
NOP
NOP
W RITE B
NOP
NOP
T7
NOP
T8
NOP
DQS,
DQS
DQ
WL = RL - 1 = 2
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 _{DIN A5 DIN A5 DIN A7} DIN B0 DIN B1 DIN B2 DIN B3 ^{DIN B4} DIN B5 DIN
SBW_BL8
The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL /
2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are acti-
vated.
Page 38
Rev. 1.02 May 2004
INFINEON Technologies