HYB18T256400AF Datasheet, PDF (65/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
5.2 DC & AC Logic Input Levels
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the
EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The
method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing
relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinc-
tion in timing methods is verified by design and characterization but not subject to production test. In single ended
mode, the DQS (and RDQS) signals are internally disabled and don’t care.
5.2.1 Single-ended DC & AC Logic Input Levels
Symbol
VIH (dc)
VIL (dc)
VIH (ac)
VIL (ac)
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
Min.
VREF + 0.125
- 0.3
VREF + 0.250
-
Max.
Units
VDDQ + 0.3
V
VREF - 0.125 V
-
V
VREF - 0.250 V
5.2.2 Single-ended AC Input Test Conditions
Symbol
Condition
VREF
Input reference voltage
VSWING(max) ^{Input signal maximum peak to peak swing}
SLEW
Input signal minimum slew rate
Value
0.5 * VDDQ
1.0
1.0
Units
V
V
V / ns
Notes
1, 2
1, 2
3, 4
1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh.
2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and
the range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure.
4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac)
to VIL(ac) on the negative transitions.
Start of Falling Edge Input Timing
V_SWING(MAX)
delta TF
Falling Slew = ^{VIH(dc) min - VIL(ac) max}
delta TF
Start of Rising Edge Input Timing
delta TR
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Rising Slew = ^{VIH(ac) min - VIL(dc) max}
delta TR
Page 65
Rev. 1.02 May 2004
INFINEON Technologies