HYB18T256400AF Datasheet, PDF (26/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
ODT timing mode switch
When entering the Power Down Modes “Slow Exit” Active Power Down and Precharge Power Down two addi-
tional timing parameters (tANPD and tAXPD) define if synchronous or asynchronous ODT timings have to be
applied.
Mode entry:
As long as the timing parameter tANPDmin is satisfied when ODT is turned on or off before entering these power-
down modes, synchronous timing parameters can be applied. If tANPDmin is not satisfied, asynchronous timing
parameters apply
CK, CK
CKE
T-5
T-4
T-3
T-2
T-1
T0
T1
T2
tANPD (3 tck)
t_IS
ODT turn-off, tANPD >= 3 tck :
ODT
ODT turn-off, tANPD <3 tck :
ODT
ODT turn-on, tANPD >= 3 tck :
ODT
ODT turn-on, tANPD < 3 tck :
ODT
t_IS
RTT
tAOFD
Synchronous
timings apply
RTT
tAOFPDmax
Asynchronous
timings apply
t_IS
tAOND
t_IS
RTT
Synchronous
timings apply
tAONPDmax
RTT
ODT03
Asynchronous
timings apply
Page 26
Rev. 1.02 May 2004
INFINEON Technologies