HYB18T256400AF Datasheet, PDF (34/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD R E A D A
NOP
NOP
DQS,
DQS
DQ's
CL = 3
RL = 3
NOP
NOP
<= tDQSCK
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4
T0
T1
T3
T4
T5
T6
T7
T8
CK, CK
NOP
BRead303
T9
CMD
P osted CAS
READ A
DQS,
DQS
DQ
NOP
NOP
BL/2 + 2
Posted CAS
W RITE A
NOP
NOP
NOP
RL = 5
WL = RL - 1 = 4
Dout A0 Dout A1 Dout A2 Dout A3
NOP
NOP
Din A0 Din A1 Din A2 Din A3
BRBW514
The minimum time from the burst read command to the burst write command is defined by a read-to-write turn-
around time, which is BL/2 + 2 clocks.
Page 34
Rev. 1.02 May 2004
INFINEON Technologies