HYB18T256400AF Datasheet, PDF (36/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.6.4 Burst Write Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of
the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read
latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a
time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising
edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subse-
quent burst bit data are issued on successive edges of the DQS until the burst length is completed. When the
burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the
burst write operation is complete. The time from the completion of the burst write to bank precharge is named
“write recovery time” (tWR) and is the time needed to store the write data into the memory array. tWR is an analog
timing parameter (see the AC table in this specification) and is not the programmed value for WR in the MRS.
Basic Burst Write Timing
DQS,
DQS
t _DQSH t DQSL
DQS
DQS
t WPRE
Din
Din
Din
t _DS
t _DH
t _WPST
Din
Example:.
Burst Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD Post CAS
W R ITE A
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL-1 = 4
NOP
NOP
<= tDQSS
NOP
NOP
Com pletion of
the Burst W rite
P re c h a rg e
tW R
DIN A0 DIN A1 DIN A2 DIN A3
BW543
Page 36
Rev. 1.02 May 2004
INFINEON Technologies