HYB18T256400AF Datasheet, PDF (53/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.9 Refresh
DDR2 SDRAM requires a refresh of all rows in any rolling 64 ms interval. The necessary refresh can be generated
in one of two ways: by explicit Auto-Refresh commands or by an internally timed Self-Refresh mode.
2.9.1 Auto-Refresh Command
Auto-Refresh is used during normal operation of the DDR2 SDRAM’s. This command is non persistent, so it must
be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller.
This makes the address bits”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-
Refresh cycles at an average periodic interval of tREFI (maximum).
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-
Refresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (t_RP)
before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the
refresh cycle. No control of the external address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay
between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command
must be greater than or equal to the Auto-Refresh cycle time (t_RFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM,
meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh
command is 9 * tREFI.
T0
T1
T2
CK, CK
CKE
"high"
> = t_RP
CMD P recharg e
NOP
NOP
T3
> = t_RFC
AUTO
REFRESH
NOP
AUTO
REFRESH
> = t_RFC
NOP
NOP
ANY
AR
Page 53
Rev. 1.02 May 2004
INFINEON Technologies