HYB18T256400AF Datasheet, PDF (18/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables
ODT (On-Die termination) and sets the Rtt value. A3~A5 are used for additive latency settings and A7 ~ A9
enables the OCD impedance adjustment mode. A10 enables or disables the differential DQS and RDQS signals,
A11 disables or enables RDQS. Address bit A12 have to be set to “low” for normal operation. With A12 set to
“high” the SDRAM outputs are disabled and in Hi-Z. “High” on BA0 and “low” for BA1 have to be set to access the
EMRS(1). A13 and all “higher” address bits (including BA2) have to be set to “low” for compatibility with other
DDR2 memory products with higher memory densities. Refer to the table for specific codes on the previous page.
Single-ended and Differential Data Strobe Signals
The following table lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by
A10 & A11 address bits in EMRS(1). RDQS and RDQS are available in x8 components only. If RDQS is enabled
in x8 components, the DM function is disabled. RDQS is active for reads and don’t care for writes:
EMRS(1)
A11
(RDQS Enable)
A10
(DQS Enable)
0 (Disable)
0 (Enable)
0 (Disable)
1 (Disable)
1 (Enable)
0 (Enable)
1 (Enable)
1 (Disable)
Strobe Function Matrix
RDQS/DM RDQS
DQS
DM
DM
RDQS
RDQS
Hi-Z
Hi-Z
RDQS
Hi-Z
DQS
DQS
DQS
DQS
DQS
DQS
Hi-Z
DQS
Hi-Z
Signaling
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering
Self-Refresh operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the
DLL is reset, 200 clock cycles must occur before a Read command can be issued to allow time for the internal
clock to be synchronized with the external clock. Less clock cycles may result in a violation of the tAC or tDQSCK
parameters.
Output Disable (Qoff)
Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the
EMRS(1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM out-
puts allows users to measure IDD currents during Read operations, without including the output buffer current.
Page 18
Rev. 1.02 May 2004
INFINEON Technologies