HYB18T256400AF Datasheet, PDF (12/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
CKE
CK
CK
CS
WE
CAS
RAS
AP
Mode
Registers
15
15
15
A0-A12,
BA0, BA1
15
2
2
9 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 128 x 64)
Sense Amplifiers
I/O Gating
DM Mask Logic
128
(x64)
Column
Decoder
7
COL0
2
Data
64
64
64
16
16
16
16
16
DQS
Generator
COL0,1 _Input
Register
Write ^{Mask 2}
2
FIFO
&
2
2
Drivers
2
2
8
2
2
1
DQS
DQS
2
16
16
64
16
Data ₁₆
16
16
16
16
16
CK,
CK
COL0,1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation
of the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
LDQ0-LDQ7
LDM
UDQ0-UDQ7
UDM
LDQS
LDQS
UDQS
UDQS
Block Diagram 4Mbit x 16 I/O x 4 Internal Memory Banks
(16Mb x 16 Organisation with 13 Row, 2 Bank and 9 Column External Addresses)
Page 12
Rev. 1.02 May 2004
INFINEON Technologies