HYB18T256400AF Datasheet, PDF (46/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.7.2 Burst Write followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay
must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.
This delay is known as a write recovery time (t WR) referenced from the completion of the burst write to the Pre-
charge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not
support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this
datasheet) and is not the programmed value for tWR in the MRS.
Examples:.
Burst Write followed by Precharge: WL = (RL - 1) = 3, BL = 4, tWR = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
W R ITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
P re c h a rg e
A
DQS,
DQS
WL = 3
Com pletion of
the Burst W rite
tW R
DQ
DIN A0 DIN A1 DIN A2 DIN A3
BW-P3
Burst Write followed by Precharge: WL = (RL - 1) = 4, BL = 4, tWR = 3
T0
T1
T2
CK, CK
CMD Post CAS
W RITE A
NOP
NOP
DQS,
DQS
DQ
WL = 4
T3
T4
T5
T6
T7
T9
NOP
NOP
NOP
NOP
NOP
P re ch a rg e
A
Com pletion of
the Burst W rite
tW R
DIN A0 DIN A1 DIN A2 DIN A3
BW-P4
Page 46
Rev. 1.02 May 2004
INFINEON Technologies