HYB18T256400AF Datasheet, PDF (11/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
CKE
CK
CK
CS
WE
CAS
RAS
AP
Mode
Registers
15
15
15
A0-A12,
BA0, BA1
15
2
2
10 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192x256x32)
Sense Amplifiers
I/O Gating
DM Mask Logic
256
(x32)
Column
Decoder
8
COL0,1
2
Data
32
32
32
8
8
8
8
8
DQS
Generator
COL0,1 _Input
Register
Write ^{Mask 1}
1
FIFO
&
1
1
Drivers
1
1
4
1
1
1
DQS
DQS
1
8
8
32
8
Data ₈
8
8
8
8
8
CK,
CK
COL0,1
DQ0-DQ7,
DM
DQS
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Block Diagram 8Mbit x 8 I/O x 4 Internal Memory Banks
(32Mb x 8 Organisation with 13 Row, 2 Bank and 10 Column External Addresses)
Page 11
Rev. 1.02 May 2004
INFINEON Technologies