HYB18T256400AF Datasheet, PDF (10/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

1.6 Block Diagrams
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
CKE
CK
CK
CS
WE
CAS
RAS
AP
Mode
Registers
15
15
15
A0-A12,
BA0, BA1
15
2
2
11 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 512 x 16)
Sense Amplifiers
I/O Gating
DM Mask Logic
512
(x16)
Column
Decoder
9
COL0,1
2
Data
16
16
16
4
4
4
4
4
DQS
Generator
COL0,1 _Input
Register
Write ^{Mask 1}
1
FIFO
&
1
1
Drivers
1
1
4
1
1
2
DQS
DQS
1
4
4
16
4
Data ₄
4
4
4
4
4
CK,
CK
COL0,1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Block Diagram 16Mbit x 4 I/O x 4 Internal Memory Banks,
(64 Mbit x 4 Organisation with 13 Row, 2 Bank and 11 Column External Addresses)
DQ0-DQ3,
DM
DQS
DQS
Page 10
Rev. 1.02 May 2004
INFINEON Technologies