HYB18T256400AF Datasheet, PDF (44/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
READ A
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clks
NOP
AL = 2
RL = 5
> = tR A S
CL = 3
>=tR C
> = tR T P
P re c h a rg e
NOP
tR P
NOP
Bank A
A c tiv a te
Dout A0 Dout A1 Dout A2 Dout A3
CL = 3
NOP
BR-P523
Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP <= 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
READ A
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clocks
NOP
AL = 2
RL = 6
> = tR A S
CL = 4
> = tR C
> = tR T P
P re ch a rg e
A
NOP
tR P
NOP
NOP
Bank A
A c tiv a te
CL = 4
Dout A0 Dout A1 Dout A2 Dout A3
BR-P624
Page 44
Rev. 1.02 May 2004
INFINEON Technologies