HYB18T256400AF Datasheet, PDF (20/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every
calibration mode command should be followed by “OCD calibration mode exit” before any other command being
issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be
carefully controlled depending on system environment.
Start
MRS should be set before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
EMRS: OCD calibration mode exit
EMRS: Drive (1)
DQ & DQS High; DQS Low
EMRS: Drive(0)
DQ & DQS Low; DQS High
ALL OK
Test
Need Calibration
EMRS: OCD calibration mode exit
ALL OK
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS :
Enter Adjus t Mode
EMRS :
Enter Adjust Mode
BL=4 cod e inpu t to all DQs
Inc, Dec, or NOP
BL =4 code input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
En d
Page 20
Rev. 1.02 May 2004
INFINEON Technologies