HYB18T256400AF Datasheet, PDF (55/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.10 Power-Down
Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is
not allowed to go low while mode register or extended mode register command time, or read or write operation is
in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Pre-
charge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those
operations.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation. DRAM design guarantees it’s DLL in a locked state with any CKE
intensive operations as long as DRAM controller complies with DRAM specifications.
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For
Active Power-down two different power saving modes can be selected within the MRS register, address bit A12.
When A12 is set to “low” this mode is referred as “standard active power-down mode” and a fast power-down exit
timing defined by the tXARD timing parameter can be used. When A12 is set to “high” this mode is referred as a
power saving “low power active power-down mode”. This mode takes longer to exit from the power-down mode
and the tXARDS timing parameter has to be satisfied.
Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is
disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled dur-
ing fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at
the inputs of the DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9
times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect com-
mand). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after
CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet.
Power-Down Entry
Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be
entered after a Precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode
after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied.
Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept
high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with
Auto-Precharge command is allowed after RL + BL/2 is satisfied.
Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress.
In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied.
In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge
command has been executed, which is WL + BL/2 + WR starting from the write with Auto-Precharge command. In
case the DDR2 SDRAM enters the Precharge Power-down mode.
Page 55
Rev. 1.02 May 2004
INFINEON Technologies