HYB18T256400AF Datasheet, PDF (7/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
1.4.2 Package Pinout for x8 components, 60 pins, FBGA Package (top view)
1
2
3
7
8
9
VDD
NU,
RDQS
VSS
A
VSSQ DQS VDDQ
DQ6
VSSQ
DM,
RDQS
B
DQS VSSQ DQ7
VDDQ DQ1 VDDQ
C
VDDQ DQ0 VDDQ
DQ4 VSSQ DQ3
D
DQ2 VSSQ DQ5
VDDL VREF VSS
E
VSSDL CK
VDD
CKE
WE
F
RAS
CK
ODT
RFU
BA0
BA1
G
CAS
CS
A10
A1
H
A2
A0
VDD
VSS
A3
A5
J
A6
A4
A7
A9
K
A11
A8
VSS
VDD
A12 NC,(A14)
L
NC,(A15) NC,(A13)
Notes:
1) RDQS / RDQS are enabled by EMRS(1) command.
2) If RDQS / RDQS is enabled, the DM function is disabled
3) When enabled, RDQS & RDQS are used as strobe signals during reads.
4) VDDL and VSSDL are power and ground for the DLL. They are isolated on the
device from VDD, VDDQ, VSS and VSSQ.
5) NC,(A13), NC,(A14) and NC,(A15) are additional address pins for future generation
DRAMs and are not connected on this component.
6) Ball position G1 “RFU” will be used for BA2 on 1Gbit memory densities and higher
Page 7
Rev. 1.02 May 2004
INFINEON Technologies