HYB18T256400AF Datasheet, PDF (56/90 Pages) Infineon Technologies AG – 256 Mbi t DDR2 SDRAM

HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Examples:
Active Power-Down Mode Entry and Exit after an Activate Command
T0
T1
T2
CK, CK
C M D _{A ctivate}
CKE
NOP
NOP
tIS
Active
Power-Down
Entry
Tn
Tn+1
Tn+2
NOP
NOP
NOP
V alid
Command
tIS
tXARD or
tXARDS *)
Active
Power-Down
Exit
Act.PD 0
note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.
Active Power-Down Mode Entry and Exit after a Read Command: RL = 4 (AL = 1, CL =3), BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn+1
Tn+2
CK, CK
CMD
READ
READ w/AP
NOP
NOP
NOP
CKE
DQS,
DQS
DQ
AL = 1
CL = 3
RL = 4
RL + BL/2
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3
NOP
NOP
tIS
NOP
NOP
V a lid
Comm and
tIS
tXARD or
tXARDS *)
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 1
note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.
Page 56
Rev. 1.02 May 2004
INFINEON Technologies