PXF4336 Datasheet, PDF (59/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Functional Description
3.2.8 Reset System
The ABM-P provides three different reset sources, as shown in Figure 3-9. The
hardware signal RESET affects the entire device. The self-clearing software reset bit
‘SWRES’ in register “MODE1” on Page 373 also affects the entire device. The software
reset bit ‘ERCSWRES’ in register “MODE1” on Page 373 affects only the ERC unit.
This bit is not self-clearing and allows the entire ERC unit to be kept in reset state while
the rest of the device is working.
Hardware reset as well as software reset bit ‘SWRES’ completely initialize the device
into power-on reset state.
Test/ SSRAM _ARC
Clocks
IF
SDRAM Interface (up)
Cell Handler upstream
ERC
AAL5
Buffer
Manager
(BM)
Queue
Scheduler
(QS)
BSCAN/
SPI
uP IF
Cell Handler downstream
QCI
IF
SDRAM Interface (dn)
ARC
bit 15
bit 14
SWRES ERC
SWRES
Register ‘MODE 1’
Figure 3-9 Reset System Overview
Note: Initialization of external and internal RAM must be started by software via
command bits ‘INITRAM’ and ‘INITSDRAM’ in register “MODE1” on Page 373
following the device reset.
Data Sheet
59
2001-12-17