PXF4336 Datasheet, PDF (333/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 96 ERCM0
AVT Table Access Mask Register 0
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
ERCM0
CC_H
Written by CPU to control internal table Read/Write
access
Bit
15
14
13
12
11
10
9
8
ERCM0(15:8)
Bit
7
6
5
4
3
2
1
0
ERCM0(7:0)
ERCM0(15:0)
ERC Mask Register 0
ERC Mask Registers 0..1 control the Write access from transfer
registers ERCT0 and ERCT1 to the internal AVT table on a per-bit
selection basis. The mask register bit positions correspond to the
respective transfer registers ERCT0 and ERCT1:
0
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
1
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
Data Sheet
333
2001-12-17