PXF4336 Datasheet, PDF (284/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 60 MASK4/MASK5
Table Access Mask Registers 4/5
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
MASK4
59_H
MASK5
5A_H
Written by CPU to control internal table Read/Write
access
Bit
15
14
13
12
11
10
9
8
MASK(15:8)
Bit
7
6
5
4
3
2
1
0
MASK(7:0)
MASK4(15:0)
MASK5(15:0)
Mask Register 4
Mask Register 5
Mask Registers 0..6 control the Write access from the respective
transfer registers to the internal tables on a per-bit selection basis.
The mask registers correspond to the respective transfer registers
(LCI0..LCI2, TCT0..TCT3, QCT0..6, SBOC0..SBOC4,
MGT0..MGT2):
0
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
1
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
Data Sheet
284
2001-12-17