PXF4336 Datasheet, PDF (229/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

7.2.8 QCI Control Registers
ABM-P
PXF 4336 V1.1
Register Description
Register 30 DQCIC
Downstream Queue Congestion Indication Control Register
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0080_H
DQCIC
35_H
Written by CPU
Bit
15
14
13
12
11
10
9
8
Unused(15:8)
Bit
7
6
5
4
3
2
1
0
FSEN BSEN
BPLEN(1:0)
QCIHYS(3:0)
FSEN
BSEN
BPLEN(1:0)
Data Sheet
Frame Sync Enable
This bit enables frame sync operation controlled by signal
‘QCITXFRAME’.
0
Frame Sync Operation disabled. Input signal
‘QCITXFRAME’ is ignored.
1
Frame Sync Operation enabled.
An active high edge at input signal ‘QCITXFRAME’
starts transmission of a new pattern.
Bit-Stuffing Enable
This bit enables HDLC bit-stuffing within the transmission pattern.
0
Bit-stuffing disabled.
1
Bit-stuffing enabled.
Bit-Pattern Length
This bit field determines the bit pattern payload length depending on
the number of queues that need to be monitored.
00
1k bits (queues 0..1023 are monitored)
01
2k bits (queues 0..2047 are monitored)
229
2001-12-17