PXF4336 Datasheet, PDF (296/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

7.2.20
ABM-P
PXF 4336 V1.1
Register Description
Queue Parameter Table Transfer Registers
Internal Table 8: Queue Parameter Table 1 Transfer Registers
Queue Parameter Table Transfer Registers are used to access the internal Upstream
and Downstream Queue Parameter Table 1 (QPT1) containing 8192 entries each. In
both Table 7-18 and Table 7-19 provide an overview of the registers involved. Each
QPT1 entry consists of 32 bits.
Note: The QPT1 table information is not used by the CPU beside during queue
initialization.
Table 7-18 Registers for QPT1 Upstream Table Access
31
0
QPT1 RAM entry (Upstream)
RAM Select:
15
0 15
0
15
0
UQPT1T1
UQPT1T0
MAR=10_H
Entry Select:
15
0 15
0
15
0
UQPTM1
UQPTM0
WAR (0..8191_D)
•
Table 7-19 Registers for QPT1 Downstream Table Access
31
0
QPT1 RAM entry (Downstream)
RAM Select:
15
0 15
0
15
0
DQPT1T1
DQPT1T0
MAR=18_H
Entry Select:
15
0 15
0
15
0
DQPTM1
DQPTM0
WAR (0..8191_D)
UQPT1T0 and UQPT1T1 are the transfer registers for the 32-bit entry of the upstream
QPT1 table. DQPT1T0 and DQPT1T1 are the transfer registers for the 32-bit entry of the
downstream QPT1 table. Access to high and low word are both controlled by mask
registers UQPTM0/UQPTM1 and DQPTM0/DQPTM1 respectively. The Mask registers
are shared for access to both tables QPT1 and QPT2, whereas, the transfer registers
are unique for each table.
Data Sheet
296
2001-12-17